Read the Length of a String in Arm Assembly

In the reading �Introduction to ARM Associates Linguistic communication� in the department on Data Directives, we saw how to define an array in AL .� The data directive DCB, DCW, or DCD defines an array of bytes, halfwords, and words, respectively, initialized to the values specified in the operand field of the information directive.� The size of the array is equal to the number of initial values.� An array can too be defined using the % directive, which defines an assortment of N bytes, where Northward is the value of the expression in the operand field.� This assortment can be used as an assortment of bytes, halfwords, or words, depending on how information technology is referenced (east.g., with LDRB, LDRH, or LDR).� For example,

�� BA DCB "a+b+c",0�� ;an assortment of half-dozen bytes (a character string is stored

�� one character per byte in a byte array)

�� HA DCW 31,511,�ane�� ;an array of 3 halfwords (6 bytes)

�� WA DCD 127,438687148 ;an array of ii words (8 bytes)

�� UA %�� 12�� ;an array of 12 bytes, six halfwords, iii words with

� �� every byte initialized to zero

Annotation that the Coffee (and C/C++) convention is that a character cord is e'er automatically terminated with a nada character (ASCII lawmaking for nul is 0016), just in AL nosotros must explicitly include the terminating nul.

vi.ane Constant Indexes and Subscripts

We diagram an array as a sequence of horizontal boxes (leftmost box has the lowest address) or vertical boxes (topmost box has the lowest accost).� Each box represents one byte in PM and contains the hex value that is stored in that location.� The array BA defined above would be diagrammed as

BA[0] �� BA[1] �� BA[2]�� BA[3]�� BA[4] �� BA[5]�� C reference

contents of byte in PM

BA+one

BA+2

BA+3

�BA+four

BA+5

PM accost

BA+1

BA+2

BA+3

BA+4

BA+5

AL reference

In C, an array element is referenced past suffixing its proper name with a subscript enclosed in foursquare brackets.� In AL ,an array element is referenced by suffixing its name with a plus sign followed by an index, except that an index of zero tin can be omitted.� Call back that in AL , the value of a variable proper name is its PM address, so BA+three is the PM address of the byte that is three bytes abroad from the byte whose PM address is BA.� The PM accost of the first element in an array is called its base address.� The subscript of the first element in a C assortment is always zero and the index of the first chemical element in an AL array is also ever zero.

It appears that an index is the same as the corresponding subscript.� This is truthful only for byte arrays.� In C, subscripts count array elements, while in AL , indexes count bytes.� Thus for byte arrays, indexes and subscripts are equal.� In halfword and word arrays nonetheless, each element is two bytes and four bytes respectively.� For example, the array HA divers higher up would exist diagrammed as

HA[0]�� HA[1]�� HA[two]��

contents of byte in PM

HA+1

HA+2

HA+3

HA+4

HA+5

PM address

HA+2

HA+4

AL reference

Since each box in an array diagram is ane byte, in the diagram for a halfword array each element is a pair of boxes.� The ARM is petty-endian, so the get-go of the two boxes in a pair is the lo byte of the halfword and the 2nd box in

the pair is the hullo byte of the halfword.� Thus, the element whose Java subscript is 1 occupies the two bytes in PM at addresses HA+2 and HA+3, with its lo byte in HA+two.� In AL , a multi-byte unit of measurement is ever referenced using the PM address of the lo byte of the unit.� In AL , the element HA[1] is referenced by HA+2, which is the PM address of its lo byte.� The array WA defined above would be diagrammed as

��

WA[0]

WA[1]

Java reference

PM contents

��

WA+i

WA+ii

WA+3

WA+4

WA+v

WA+6

WA+vii

PM address

A word is iv bytes, so the PM addresses of successive elements differ past four.� In general, the AL reference corresponding to the C reference A[con], where con is a constant, is A+thou, where m is con multiplied by the length of the elements in A.� In other words, the index corresponding to an assortment subscript equals the subscript multiplied by the number of bytes in the elements of the assortment.

6.2 Variable Indexes and Subscripts

Ane might jump to the incorrect conclusion that the AL reference corresponding to the C reference A[i], where i is a variable, would be A+i.� This does not work considering arithmetics expressions in AL are evaluated by the assembler earlier the plan is really executed.� Thus, every chemical element in an AL expression must be a abiding or the name of a constant.� The expression A+i in an educational activity such every bit

�� LDR� R0,A+i

would be evaluated by the assembler as a PM address y� =� add(A)+add(i) and y would be put in the LDR didactics as the address of the word to load into annals R0.� It is unlikely that y will exist the address of any element in the assortment A.� Furthermore, no thing how the value of i changes during execution of the plan, the PM location referenced by this LDR instruction will ever be y, that is, it volition ever reference the same PM location.� In lodge to get the effect of a variable subscript during execution of a program, we need to be able to modify the address an instruction uses to reference PM.

The simplest mechanism for varying the address used by an didactics is indexed addressing.� In the ARM we put the array'due south base of operations address in 1 register, chosen the base register, and the index in some other register, called the index register.� For instance, suppose the base address of the array BA, which is defined in a higher place, is in R5 and the alphabetize is in R6.� Then the instruction

�� LDRB� R0,[R5,R6]

will load the byte whose PM address equals cont(R5)+cont(R6) into the lo byte of R0.� So if the contents of R6 is varied from 0 to 5 by increments of one, the LDRB instruction will refer to each of the elements BA[0] through BA[five] in plow.� Sequencing through the elements of HA or WA is essentially the aforementioned except that the contents of the index annals must be incremented by two or 4, respectively, instead of one (and also the base of operations register must contain the base address of HA or WA).� The amount by which a variable index is incremented (or decremented) is equal to the number of bytes in the assortment elements.� To get the base accost of an array Aname into a register, we use one of the post-obit

�� ADR�� R5,Aname

�� ADRL� R5,Aname

�� LDR�� R5,=Aname

ADR can simply exist used when the base of Aname is inside 255 bytes, if not word-aligned, or 1020 bytes, if word-aligned, of the ADR educational activity.� The assembler generates ane of the post-obit instructions

�� Add together� R5,PC,#con

�� SUB� R5,PC,#con

where con is such that when appropriately shifted and added to, or subtracted from, the current contents of PC, the result is the base address of Aname.� If the assembler is unable to do this, it volition indicate an fault and ane of the

other forms must be used.� ADRL can only be used when the base of Aname is within 64K bytes, if not word-aligned, or 256K bytes, if discussion-aligned, of the ADRL instruction.� The ADRL always generates ii ML instructions that combine the hi and lo eight bits of the distance between the ADRL and the array base, by shifting and adding to or subtracting from the PC contents to form the address of Aname.� If neither of these forms works, and then

�� LDR� R5,=Aname

must exist used.� This form is the slowest because the address is stored in PM as a 32-scrap constant, not synthetic from immediate information in the instructions equally it is for both ADR and ADRL.

6.3 Indexing and Arrays

Suppose A is a byte array, B a halfword array, and C a word array.� If the loop variable is kept in a register then it can be directly used as the alphabetize.� For example, to sum the elements in A modulo 2⁸, assuming they are naturals�

�� Sum = 0;�� MOV� R0,#0

�� for ( i = 0; i <= 5; i++ )�� ADR� R5,A

�� MOV� R6,#0

�� {�� AGN� CMP� R6,#v

�� BHI� NXT

�� Sum = Sum+A[i];�� LDRB R1,[R5,R6]

�� Add together� R0,R0,R1

�� }�� ADD� R6,R6,#1

�� B�� AGN

�� NXT� STRB R0,Sum

Annotation that an index is always 32 bits.� To sum the elements in B modulo 2¹⁶, assuming they are integers

�� Sum = 0;�� MOV�� R0,#0

�� for ( i = 0; i <= five; i++ )�� ADR�� R5,B

�� MOV ��R6,#0

�� {�� AGN� CMP�� R6,#10

�� BHI�� NXT

�� Sum = Sum+B[i];�� LDRSH R1,[R5,R6]

�� ADD�� R0,R0,R1

�� }�� Add�� R6,R6,#2

�� B�� AGN

�� NXT� STRH� Sum

and to sum the elements in C modulo 2³²

�� Sum = 0;� ��MOV� R0,#0

�� for ( i = 0; i <= 5; i++ )�� ADR� R5,C

�� MOV� R6,#0

�� {�� AGN� CMP� R6,#20

�� BHI� NXT

�� Sum = Sum+C[i];�� LDR� R1,[R5,R6]

�� ADD� R0,R0,R1

�� }�� ADD� R6,R6,#4

�� B�� AGN

�� NXT� STR� Sum

Comparing the three code sequences, the only difference is the amount by which the index register (R6) is incremented, the instructions used to load and shop the array elements, and of course the address that is loaded into the base register (R5).

6.iv Register Indirect Addressing

This section applies only to the memory reference in load and shop instructions, such as in

�� LDR� Rd,memref

�� STRB Rs,memref

Unless stated otherwise, all comments apply as to all of the load and store instructions, even though we will apply only LDR in our examples.� Nosotros carve up the load and store instructions into ii groups: grouping LS1 consists of the� LDR,� LDRB,� STR, and STRB instructions and group LS2 consists of the LDRSB,� LDRH,� LDRSH, and STRH instructions.� Every reference to PM in AL is some variant of annals indirect addressing.� The basic class of memref in register indirect addressing is [Rb], as in

�� (ane)�� LDR� Rd,[Rb]

where Rb contains the PM address of some entity, which is commonly a variable or the base of an array.� The address of the referenced memory location is the address in Rb.� So if Rb contains the address of C, the current value of C is loaded into Rd.� One variant of this form is

�� (2)�� LDR� Rd,[Rb�#exp]

Here, the assembler evaluates exp, which must result in a constant offset (off) that is less than 2¹² for group LS1 instructions or less than 2^eight for group LS2 instructions.� This constant is inserted into the LDR pedagogy and the accost of the referenced PM location is cont(Rb)�off.� The form

�� (3)�� LDR� Rd,C

is really simply annals indirect addressing using PC equally the base of operations register, that is, writing C is equivalent to writing [PC�#off(PC,C)], where off(PC,C) is the offset of C from the current contents of PC.� Computing off(PC,C) is rather tricky and thankfully the assembler does information technology for you.� If it is unable to do and then, information technology will signal an error.� In this example, the address of C� must� be� loaded� into� a� register� Rb and and so basic annals indirect addressing [Rb]� is� used.�� I variant of this form is

�� (4)�� LDR� Rd,C�exp

Here, writing C�exp is equivalent to writing [PC�#off(PC,C)�exp].

In group LS1 instructions, indexed addressing is written as

�� (5)�� LDR� Rd,[Rb,{�}Rx{,ShiftType#ShiftAmount}]

where ShiftType is i of LSL, LSR, ASR, ROR, or RRX and ShiftAmount is an abiding expression whose value is less than 25.� If a shift blazon and amount are included, the contents of Rx is shifted before being added to the contents of Rb and the accost of the referenced PM location is cont(Rb)�shift(cont(Rx)).� Otherwise Rx is not shifted and the address of the referenced PM location is cont(Rb)�cont(Rx).� In grouping LS2 instructions, indexed addressing is written the same as for grouping LS1 instructions, except that no shifting is permitted.

Automatic incrementing or decrementing of the base register may exist optionally specified in forms (2) and (5) above.� When this is done, we call information technology autoincrement addressing or autodecrement addressing, respectively.� This option is specified past appending an assertion point (!) every bit a suffix on the memref, as in

�� (6)�� LDR� Rd,[Rb�#exp]!

�� (7)�� LDR� Rd,[Rb,{�}Rx{,ShiftType#ShiftAmount}]!

In (vi), later on using cont(Rb)�off every bit the reference address, this value replaces the original contents of Rb, that is, cont(Rb) is incremented or decremented by off.� In (vii), after using cont(Rb)�shift(cont(Rx)) every bit the reference address, this value replaces the original contents of Rb, that is, cont(Rb) is incremented or decremented past shift(cont(Rx)). Autoincrement addressing and autodecrement addressing are also known equally update addressing.

All the addressing forms discussed above are pre-indexed addressing because an alphabetize value is added to a base of operations address before being used every bit the PM reference accost.� It is as well possible to have post-indexed addressing, as in

�� (8)�� LDR� Rd,[Rb],#�exp

�� (9)�� LDR� Rd,[Rb],{�}Rx{,ShiftType#ShiftAmount}

In both forms, the address of the referenced PM location is cont(Rb).� After this value is used as the reference accost, the contents of Rb are incremented or decremented by off or shift(cont(Rx)).� Post indexed addressing is always update addressing, while pre-indexed addressing may exist update addressing or non-update addressing.

6.5 Operations on Arrays

A few elementary AL code patterns are the footing for most operations on arrays.� In Section 6.3 we saw one such pattern that summed all the elements in an assortment.� A mutual performance on an assortment that contains a cipher terminated string is to determine the length of that string.

�� i = 0;�� MOV� R6,#0

�� while ( A[i] != nul )�� ADR� R5,A

�� {�� AGN� LDRB R0,[R5,R6]

�� CMP� R0,#0

�� BEQ� NXT

�� i++;�� Add� R6,R6,#1

�� }�� B�� AGN

�� Leng = i;�� NXT� STR� R6,Leng

There is no error detection in this AL lawmaking.� If there is no nul in A, bytes across the end of A will exist tested.� In fact, if at that place is no byte anywhere in memory containing nul, the program will loop incessantly.� Why?� Addition in a reckoner is ever modulo, so when the address of A[i] reaches the highest PM address, calculation 1 results in a PM accost of zippo.� We call this modify for the highest PM address to the lowest PM address, memory wrap effectually.� Suppose the length of the array A is N, then we know the cord cannot be longer than North-2 characters (the last byte has to contain a nul character if A contains a legal null terminated string).� If we continually test for i greater than or equal to N-i, nosotros will avoid an infinite loop and fake values for the string's length.

Some other common operation on a null terminated string is to make a re-create.� Suppose the array South is the same size as the assortment A that was used in a higher place.� AL lawmaking that makes a copy of A and puts the copy in S is

�� i = 0;�� MOV� R6,#0

�� while (1)�� ADR� R5,A

�� ADR� R7,S

�� { S[i] = A[i]�� AGN� LDRB R0,[R5,R6]

�� STRB R0,[R7,R6]

�� if ( A[i] == nul ) break;�� CMP� R0,#0

�� BEQ� NXT

�� i++;�� Add� R6,R6,#1

�� }�� B�� AGN

�� NXT� ---

Here we demand to copy at least one byte since even if the string being copied is empty (i.e., no characters in the string) we demand to copy the terminating nul grapheme.

The ability to shift the contents of the index before calculation it to the contents of the base register is useful when dealing with two arrays when the size of the elements in one assortment is non the same equally the size of the elements in the other assortment.� Suppose the byte array A contains N naturals and B is a halfword assortment of the aforementioned size.� The following code squares each chemical element of A and puts the double length result into the corresponding element of B.

�� for ( i = 0; i < N; i++ )�� MOV� R4,N

�� ADR� R5,A

�� ADR� R7,B

�� MOV� R6,#0

�� {�� AGN� CMP� R6,R4

�� BHS� NXT

�� B[i] = A[i]*A[i];�� LDRB R0,[R5,R6]

�� MUL� R3,R0,R0

�� STRH R3,[R7,R6,LSL#1]

�� }�� ADD� R6,R6,#one

�� B�� AGN

�� NXT� ---

The index values used in the loop, which are in R6, go from 0 to N-1 as does the subscript in the Java lawmaking on the left.� This is the correct sequence for a byte array, only not for a halfword array where each index must exist twice the corresponding subscript.� The logical shift left by one flake (LSL#ane) in the STRH instruction multiplies the index by two, then the alphabetize sequence used to reference elements of B is 0, 2, 4, and so forth.

Update addressing is more often than not useful for saving instructions in the body of a loop and thus reducing the execution time of a program.

�� i = 0;�� ADR� R5,A

�� MOV� R4,R5

�� while ( A[i] != nul )�� AGN� LDRB R0,[R5],#+one

�� CMP� R0,#0

�� BEQ� NXT

�� i++;

�� }�� B�� AGN

�� Leng = i;�� NXT� SUB� R5,R5,R4

�� STR� R5,Leng

Hither the mail-indexed addressing, which is always update addressing, adds one to the address in R5 afterward each use of that address to reference PM.� This eliminates the need for an explicit index, and then we exercise not need R6 or the Add together instruction that explicitly incremented the index.� Adding an boosted didactics outside of the loop does not increase the execution time much, but eliminating one pedagogy inside the loop results in a pregnant saving if the loop is executed many times.

6.vi Stacks

In the ARM, a stack is an assortment of words.� Each item on the stack is one word.� The stack pointer SP (R13) always points to the elevation of the stack, that is, it contains the PM address of the item currently on the top of the stack.� In PM the stack is "upside down" with the bottom of the stack at the highest address and the elevation of the stack at the lowest accost.� For case, if the bottom of the stack is at 0007FFFC₁₆ and three items have been pushed onto the stack, it looks like

�� PM accost�� Contents

�� ????????

�� 0007FFF0�� ????????

�� 0007FFF4 3rd detail pushed�� SP current top of stack

�� 0007FFF8 second item pushed�� SP+iv

�� 0007FFFC 1st item pushed�� SP+eight

�� 00080000�� ????????�� bottom of stack

When the stack is empty, SP will contain the accost of the word immediately higher up the word at the bottom of the stack, hither 00080000.� Two common operations on a stack are Push, which puts an item on the superlative of the stack, and Pop, which takes off the particular at the summit of the stack.� On the ARM, AL code to push the contents of R0 onto the stack is

� STR R0,[SP,#-four]!

and AL code to popular the height of the stack into R1 is

�� LDR R1,[SP],#+4

To get a copy of the give-and-take on the top of the stack without popping it, use

�� LDR R1,[SP]

and to reference Nth word "downward" from the top of the stack, utilize

�� LDR R1,[SP,#iv*N]

Adjusted from � 2000 Robert Grand. Graham��

groveyousight.blogspot.com

Source: https://www.mtholyoke.edu/courses/dstrahma/cs221/olr/olr7.htm

Read the Length of a String in Arm Assembly

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